A High Speed, Optimized Multiplier Architecture for a DF-ECC Processor
نویسندگان
چکیده
This paper presents a High speed, optimized multiplier architecture for a dual-field (DF) processor for elliptic curve cryptography (ECC). This processor can support the required operations in both galois prime field GF(p) and binary field GF(2). The performance of the processor is enhanced by the judicious selection of proper type of coordinates in the arithmetic unit. The arithmetic unit is designed to provide dual-field multiplication and addition. The FPGA synthesis results show that the proposed dual-field ECC processor with Karatsuba method can reach a speed up to 124 MHz, consumes a power of 1091mW and occupies 3066 slices.
منابع مشابه
Optimized Arithmetic Modules of a Rsd-based Ecc Processor
The design strategy is focused fully on modular arithmetic modules rather than overall elliptic curve cryptography processor architecture. The processor has an efficient modular adder to reduce carry propagation problem, a high throughput modular divider which results in maximum operating frequency and modular multiplier in the processor is optimized based on throughput and modular reduction. T...
متن کاملSpace Optimized Multiplier Architecture for Embedded Cryptoprocessor
The finite field modular multiplier is the most critical component in the elliptic curve crypto processor (ECCP) consuming the maximum chip area and contributing the most to the device latency. Modular multiplication, point multiplication, point doubling are few of the critical activities to be carried out by multiplier in ECC algorithm, and should be managed without compromising on security an...
متن کاملModified 32-Bit Shift-Add Multiplier Design for Low Power Application
Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. ...
متن کاملLow Settling Time All Digital DLL For VHF Application
Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...
متن کاملA High-Speed Design of Montgomery Multiplier
With the increase of key length used in public cryptographic algorithms such as RSA and ECC, the speed of Montgomery multiplication becomes a bottleneck. This paper proposes a high speed design of Montgomery multiplier. Firstly, a modified scalable high-radix Montgomery algorithm is proposed to reduce critical path. Secondly, a highradix clock-saving dataflow is proposed to support high-radix o...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2014